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for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 1 HMCAD1040-40 v01.0411 dual 10-bit 20/ 40 msps a /d converter functional diagram features ? 10-bit r esolution ? 20/40 m s p s maximum s ampling r ate ? ultra-low power dissipation: 24/43 mw ? 61.6 db snr @ 8 mhz ? internal r eference circuitry ? 1.8 v core s upply v oltage ? 1.7 C 3.6 v i/ o s upply v oltage ? parallel cm os o utput ? 9 x 9 mm 64-pin qf n (lp9 e ) package ? dual channel t ypical a pplications ? medical imaging ? portable t est e quipment ? digital o scilloscopes ? if communication general description t he HMCAD1040-40 is a high performance low power dual analog-to-digital converter (adc). t he adc employs internal reference circuitry, a cm os control interface, cm os output data and is based on a proprietary structure. digital error correction is employed to ensure no missing codes in the complete full scale range. s everal idle modes with fast startup times exist. e ach channel can be independently powered down and the entire chip can either be put in s tandby mode or power down mode. t he different modes are optimized to allow the user to select the mode resulting in the lowest possible energy consumption during idle mode and startup. t he HMCAD1040-40 has a highly linear t ha optimi- zed for frequencies up to n yquist. t he differential clock interface is optimized for low jitter clock sources and supports l v d s , l v p e cl, sine wave and cm os clock inputs. pin compatible with hmcad1040-80, hmcad1050-40 and hmcad1050-80. figure 1. functional block diagram www.datasheet.net/ datasheet pdf - http://www..co.kr/
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 2 HMCAD1040-40 v01.0411 dual 10-bit 20/ 40 msps a /d converter e lectrical specifcations dc e lectrical specifcations a v dd= 1.8 v , d v dd= 1.8 v , d v ddck= 1.8 v , ov dd= 2.5 v , 20/40 m s p s clock, 50% clock duty cycle, -1 dbfs 8 mhz input signal, unless otherwise noted parameter condition min. t yp. max. units dc accuracy n o missing codes guaranteed o ffset error mid-scale offset 1 l s b gain error full scale range deviation from typical 6 %fs gain matching gain matching between channels. 3 sigma value at worst case conditions 0.5 %fs d n l differential nonlinearity 0.15 l s b i n l integral nonlinearity 0.2 l s b v cm common mode voltage output v a v dd/2 v analog input input common mode analog input common mode voltage v cm -0.1 v cm +0.2 v full scale range differential input voltage range 2.0 v pp input capacitance differential input capacitance 2 pf bandwidth input bandwidth 500 mhz power supply core s upply v oltage s upply voltage to all 1.8 v domain pins. s ee pin confguration and description 1.7 1.8 2.0 v i/ o s upply v oltage o utput driver supply voltage ( ov dd). s hould be higher than or equal to core s upply v oltage ( vov dd v d v dd) 1.7 2.5 3.6 v www.datasheet.net/ datasheet pdf - http://www..co.kr/
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 3 HMCAD1040-40 v01.0411 dual 10-bit 20/ 40 msps a /d converter a c e lectrical specifcations - 20 msps a v dd= 1.8 v , d v dd= 1.8 v , d v ddck= 1.8 v , ov dd= 2.5 v , fs = 20 m s p s clock, 50% clock duty cycle, -1 dbfs 8 mhz input signal, unless other - wise noted. parameter condition min. t yp. max. units performance snr s ignal to n oise r atio fi n = 2 mhz 61.7 dbf s fi n = 8 mhz 60 61.6 dbf s fi n =~ fs /2 61.6 dbf s fi n = 20 mhz 61.6 dbf s sn d r s ignal to n oise and distortion r atio fi n = 2 mhz 61.7 dbf s fi n = 8 mhz 60 61.6 dbf s fi n =~ fs /2 60.5 dbf s fi n = 20 mhz 61.6 dbf s s fd r s purious free dynamic r ange fi n = 2 mhz 80 dbc fi n = 8 mhz 70 81 dbc fi n =~ fs /2 70 dbc fi n = 20 mhz 80 dbc hd2 s econd order harmonic distortion fi n = 2 mhz -90 dbc fi n = 8 mhz -80 -90 dbc fi n =~ fs /2 -90 dbc fi n = 20 mhz -90 dbc hd3 t hird order harmonic distortion fi n = 2 mhz -80 dbc fi n = 8 mhz -70 -81 dbc fi n =~ fs /2 -70 dbc fi n = 20 mhz -80 dbc eno b e ffective number of bits fi n = 2 mhz 10.0 bits fi n = 8 mhz 9.7 9.9 bits fi n =~ fs /2 9.8 bits fi n = 20 mhz 9.9 bits crosstalk s ignal crosstalk between channels, fi n 1=8mhz, fi n 0=9.9mhz -105 db power supply analog supply current 8.2 ma digital supply current digital core supply 1.7 ma o utput driver supply 2.5 v output driver supply, sine wave input, fi n = 1 mhz, ck_ e x t enabled 2.8 ma o utput driver supply 2.5 v output driver supply, sine wave input, fi n = 1 mhz, ck_ e x t disabled 2.3 ma analog power dissipation 14.8 mw digital power dissipation ov dd = 2.5 v , 5pf load on output bits, fi n = 1 mhz, ck_ e x t disabled 8.8 mw t otal power dissipation ov dd = 2.5 v , 5pf load on output bits, fi n = 1 mhz, ck_ e x t disabled 23.6 mw power down dissipation 9.9 mw s leep mode 1 power dissipation, s leep mode one channel 15.2 mw s leep mode 2 power dissipation, s leep mode both channels 7.7 mw clock inputs max. conversion r ate 20 m s p s min. conversion r ate 3 m s p s www.datasheet.net/ datasheet pdf - http://www..co.kr/
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 4 HMCAD1040-40 v01.0411 dual 10-bit 20/ 40 msps a /d converter a c e lectrical specifcations - 40 msps a v dd= 1.8 v , d v dd= 1.8 v , d v ddck= 1.8 v , ov dd= 2.5 v , fs = 40 m s p s clock, 50% clock duty cycle, -1 dbfs 8 mhz input signal, unless other - wise noted. parameter condition min. t yp. max. units performance snr s ignal to n oise r atio fi n = 2 mhz 61.6 dbf s fi n = 8 mhz 60 61.6 dbf s fi n =~ fs /2 61.6 dbf s fi n = 30 mhz 61.6 dbf s sn d r s ignal to n oise and distortion r atio fi n = 2 mhz 61.6 dbf s fi n = 8 mhz 60 61.6 dbf s fi n =~ fs /2 61.2 dbf s fi n = 30 mhz 61.4 dbf s s fd r s purious free dynamic r ange fi n = 2 mhz 80 dbc fi n = 8 mhz 70 81 dbc fi n =~ fs /2 72 dbc fi n = 30 mhz 80 dbc hd2 s econd order harmonic distortion fi n = 2 mhz -90 dbc fi n = 8 mhz -80 -90 dbc fi n =~ fs /2 -85 dbc fi n = 30 mhz -85 dbc hd3 t hird order harmonic distortion fi n = 2 mhz -80 dbc fi n = 8 mhz -70 -81 dbc fi n =~ fs /2 -72 dbc fi n = 30 mhz -80 dbc eno b e ffective number of bits fi n = 2 mhz 9.9 bits fi n = 8 mhz 9.7 9.9 bits fi n =~ fs /2 9.8 bits fi n = 30 mhz 9.9 bits crosstalk s ignal crosstalk between channels, f i n 1 = 8 mhz, f i n 0 = 9.9 mhz -100 db power supply analog supply current 14.4 ma digital supply current digital core supply 3.4 ma o utput driver supply 2.5 v output driver supply, sine wave input, fi n = 1 mhz, ck_ e x t enabled 5.1 ma o utput driver supply 2.5 v output driver supply, sine wave input, fi n = 1 mhz, ck_ e x t disabled 4.2 ma analog power dissipation 25.9 mw digital power dissipation ov dd = 2.5 v , 5pf load on output bits, fi n = 1 mhz, ck_ e x t disabled 16.6 mw t otal power dissipation ov dd = 2.5 v , 5pf load on output bits, fi n = 1 mhz, ck_ e x t disabled 42.5 mw power down dissipation 9.7 mw s leep mode 1 power dissipation, s leep mode one channel 25.7 mw s leep mode 2 power dissipation, s leep mode both channels 11.3 mw clock inputs max. conversion r ate 40 m s p s min. conversion r ate 3 m s p s www.datasheet.net/ datasheet pdf - http://www..co.kr/
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 5 HMCAD1040-40 v01.0411 dual 10-bit 20/ 40 msps a /d converter digital & t iming specifcations a v dd= 1.8 v , d v dd= 1.8 v , d v ddck= 1.8 v , ov dd= 2.5 v , conversion r ate: max specifed, 50% clock duty cycle, -1dbf s input signal, 5 pf capacitive load on data outputs, unless otherwise noted parameter condition min typ max unit clock inputs duty cycle 20 80 % high compliance cm os , l v d s , l v p e cl, s ine wave input range differential input swing 0.4 v pp input range differential input swing, sine wave clock input 1.6 v pp input common mode voltage keep voltages within ground and voltage of ov dd 0.3 v ov dd -0.3 v input capacitance differential 2 pf timing t pd s tart up time from power down mode to active mode 900 clock cycles t s lp s tart up time from s leep mode to active mode 20 clock cycles t ovr o ut of range recovery time 1 clock cycles t ap aperture delay 0.8 ns ?rms aperture jitter < 0.5 ps t la t pipeline delay 12 clock cycles t d o utput delay (see timing diagram). 5pf load on output bits 3 10 ns t dc o utput delay relative to ck_ e x t (see timing diagram) 1 6 ns logic inputs v hi high level input v oltage. v ov dd 3.0 v 2 v v hi high level input v oltage. v ov dd = 1.7 v C 3.0 v 0.8 v ov dd v v li low level input v oltage. v ov dd 3.0 v 0 0.8 v v li low level input v oltage. v ov dd = 1.7 v C 3.0 v 0 0.2 v ov dd v i hi high level input leakage current 10 a i li low level input leakage current 10 a c i input capacitance 3 pf logic outputs v h o high level o utput v oltage v ov dd -0.1 v v l o low level o utput v oltage 0.1 v c l max capacitive load. post-driver supply voltage equal to pre-driver supply voltage v ov dd = v o c v dd 5 pf c l max capacitive load. post-driver supply voltage above 2.25 v [1] 10 pf [1] t he outputs will be functional with higher loads. however, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents and resulting switching noise at a minimum www.datasheet.net/ datasheet pdf - http://www..co.kr/
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 6 HMCAD1040-40 v01.0411 dual 10-bit 20/ 40 msps a /d converter t iming diagram t able 1. a bsolute maximum r atings pin pin pin a v dd a vss -0.3 v to +2.3 v d v dd d vss -0.3 v to +2.3 v a vss , d vss ck, d vss , ovss d vss -0.3 v to +0.3 v ov dd ovss -0.3 v to +3.9 v ipx, i n x, analog inputs and outputs a vss -0.3 v to +2.3 v digital outputs ovss -0.3 v to +3.9 v ckp, ck n d vss ck -0.3 v to +3.9 v digital inputs ovss -0.3 v to +3.9 v o perating temperature -40 to +85 oc s torage temperature -60 to +150 oc s oldering profle qualifcation j- st d-020 e l e c trost a t ic sens i t i ve d ev ic e o b serve ha n dli n g p re cau t i ons s tresses above those listed under absolute maximum r atings may cause permanent damage to the device. t his is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. e xposure to absolute maximum rating conditions for extended periods may affect device reliability. figure 2. timing diagram www.datasheet.net/ datasheet pdf - http://www..co.kr/
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 7 HMCAD1040-40 v01.0411 dual 10-bit 20/ 40 msps a /d converter pin confguration and description figure 3. package drawing, qfn 64-pin www.datasheet.net/ datasheet pdf - http://www..co.kr/
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 8 HMCAD1040-40 v01.0411 dual 10-bit 20/ 40 msps a /d converter t able 2. pin descriptions pin n umber function description 1, 18, 23 d v dd digital and i/ o -ring pre driver supply voltage, 1.8 v 2 cm_ e x t common mode voltage output 3, 9, 12 a v dd analog supply voltage, 1.8 v 4, 5, 8 a vss analog ground 6, 7 ip0, i n 0 analog input channel 0 (non-inverting, inverting) 10, 11 ip1, i n 1 analog input channel 1 (non-inverting, inverting) 13 d vss ck clock circuitry ground 14 d v ddck clock circuitry supply voltage, 1.8 v 15 ckp clock input, non-inverting (format: l v d s , l v p e cl, cm os / tt l, s ine wave) 16 ck n clock input, inverting. for cm os input on ckp, connect ck n to ground. 17, 64 d vss digital circuitry ground 19 ck_ e x t _ en ck_ e x t signal enabled when low (zero). t ristate when high. 20 df r m t data format selection. 0: o ffset binary, 1: t wo's complement 21 pd_ n full chip power down mode when low. all digital outputs reset to zero. after chip power up always apply power down mode before using active mode to reset chip. 22 oe _ n _1 o utput e nable channel 0. t ristate when high 24, 41, 58 ov dd i/ o ring post-driver supply voltage. v oltage range 1.7 to 3.6 v 25, 40, 57 ovss ground for i/ o ring 26 n c 27 n c 28 n c 29 d1_0 o utput data channel 1 (l s b) 30 d1_1 o utput data channel 1 31 d1_2 o utput data channel 1 32 d1_3 o utput data channel 1 33 d1_4 o utput data channel 1 34 d1_5 o utput data channel 1 35 d1_6 o utput data channel 1 36 d1_7 o utput data channel 1 37 d1_8 o utput data channel 1 38 d1_9 o utput data channel 1 (m s b) 39 orn g_1 o ut of r ange fag channel 1. high when input signal is out of range 42 ck_ e x t o utput clock signal for data synchronization. cm os levels 43 n c 44 n c 45 n c 46 d0_0 o utput data channel 0 (l s b) 47 d0_1 o utput data channel 0 48 d0_2 o utput data channel 0 49 d0_3 o utput data channel 0 www.datasheet.net/ datasheet pdf - http://www..co.kr/
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 9 HMCAD1040-40 v01.0411 dual 10-bit 20/ 40 msps a /d converter t able 2. pin descriptions pin n umber function description 50 d0_4 o utput data channel 0 51 d0_5 o utput data channel 0 52 d0_6 o utput data channel 0 53 d0_7 o utput data channel 0 54 d0_8 o utput data channel 0 55 d0_9 o utput data channel 0 (m s b) 56 orn g_0 o ut of r ange fag channel 0. high when input signal is out of range 59 oe _ n _0 o utput e nable channel 0. t ristate when high 60, 61 cm_ e x t bc_1, cm_ e x t bc_0 bias control bits for the buffer driving pin cm_ e x t 00: o ff 01: 50ua 10: 500ua 11: 1ma 62, 63 s lp_ n _1, s lp_ n _0 s leep mode 00: s leep mode 01: channel 0 active 10: channel 1 active 11: both channels active www.datasheet.net/ datasheet pdf - http://www..co.kr/
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 10 HMCAD1040-40 v01.0411 dual 10-bit 20/ 40 msps a /d converter r ecommended u sage analog input t he analog input to the HMCAD1040-40 is a switched capacitor track-and-hold amplifer optimized for differential operation. o peration at common mode voltages at mid supply is recommended even if performance will be good for the ranges specifed. t he cm_ e x t pin provides a voltage suitable as common mode voltage reference. t he internal buffer for the cm_ e x t voltage can be switched off, and driving capabilities can be changed by using the cm_ e x t bc control input. figure 4 shows a simplifed drawing of the input network. t he signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. a small external resistor (e.g. 22 o hm) in series with each input is recom- mended as it helps reduce transient currents and dampens ringing behavior. a small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. t he resistors form a low pass flter with the capacitor, and values must therefore be determined by requirements for the application. figure 4. input confguration dc-coupling figure 5. dc coupled input with buffer figure 5 shows a recommended confguration for dc- coupling. n ote that the common mode input voltage must be controlled according to specifed values. preferably, the cm_ e x t output should be used as reference to set the common mode voltage. t he input amplifer could be inside a companion chip or it could be a dedicated amplifer. s everal suitable single ended to differential driver amplifers exist in the market. t he system designer should make sure the specifcations of the selected amplifer is adequate for the total system, and that driving capabilities comply with the HMCAD1040-40 input specifcations. detailed confguration and usage instructions should be found in the documentation of the selected driver, and the values given in fgure 5 must be varied according to the recommendations for the driver. ac-coupling a signal transformer or series capacitors can be used to make an ac-coupled input network. figure 6 shows a recommended confguration using a transformer. make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. t he bandwidth should exceed the sampling rate of the adc with at least a factor of 10. it is also important to minimize phase mismatch between the differential adc inputs for good hd2 performance. t his type of transformer coupled input is the preferred confguration for high frequency signals as most differential amplifers do not have adequate performance at high frequencies. magnetic coupling between the transformers and pcb traces may impact channel crosstalk, and must be taken into account during pcb layout. if the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the adc will also travel along this distance. if these kick-backs are not terminated properly at the source side, they are refected and will add to the input signal at the adc input. t his could reduce the adc performance. t o avoid this effect, the source must effectively terminate the adc kick-backs, or the traveling distance should be very short. if this problem could not be avoided, the circuit in fgure 8 can be used. figure 6. transformer coupled input www.datasheet.net/ datasheet pdf - http://www..co.kr/
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 11 HMCAD1040-40 v01.0411 dual 10-bit 20/ 40 msps a /d converter figure 7 shows ac-coupling using capacitors. r esistors from the cm_ e x t output, r cm, should be used to bias the differential input signals to the correct voltage. t he series capacitor, ci, form the high- pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. figure 7. ac coupled input figure 8. alternative input network n ote that startup time from s leep mode and power down mode will be affected by this flter as the time required to charge the series capacitors is dependent on the flter cut-off frequency. if the input signal has a long traveling distance, and the kick-backs from the adc not are effectively terminated at the signal source, the input network of fgure 8 can be used. t he confguration in fgure 8 is designed to attenuate the kickback from the adc and to provide an input impedance that looks as resistive as possible for frequencies below n yquist. v alues of the series inductor will however depend on board design and conversion rate. in some instances a shunt capacitor in parallel with the termination resistor (e.g. 33 pf) may improve adc performance further. t his capacitor attenuates the adc kick-back even more, and minimizes the kicks traveling towards the source. however, the impedance match seen into the transformer becomes worse. clock input and jitter considerations t ypically high-speed adcs use both clock edges to generate internal timing signals. in the HMCAD1040-40 only the rising edge of the clock is used. hence, input clock duty cycles between 20% and 80% are acceptable. t he input clock can be supplied in a variety of formats. t he clock pins are ac-coupled internally. hence a wide common mode voltage range is accepted. differential clock sources as l v d s , l v p e cl or differential sine wave can be connected directly to the input pins. for cm os inputs, the ck n pin should be connected to ground, and the cm os clock signal should be connected to ckp. for differential sine wave clock, the input amplitude must be at least 800 m v pp. t he quality of the input clock is extremely important for high-speed, high-resolution adcs. t he contribution to snr from clock jitter with a full scale signal at a given frequency is shown in equation 1, snr jitter = 20 log (2 ? in ? t ) (1) where fi n is the signal frequency, and t is the total rms jitter measured in seconds. t he rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal adc circuitry. for applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. t his can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifcations) and make sure the clock distribution is well controlled. it might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. it is of utmost importance to avoid crosstalk between the adc output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. t he jitter performance is improved with reduced rise and fall times of the input clock. hence, optimum jitter performance is obtained with l v d s or l v p e cl clock with fast edges. cm os and sine wave clock inputs will result in slightly degraded jitter performance. if the clock is generated by other circuitry, it should be re-timed with a low jitter master clock as the last operation before it is applied to the adc clock input. digital outputs digital output data are presented in parallel cm os form. t he voltage on the ov dd pin sets the levels of the cm os outputs. t he output drivers are dimensioned to drive a wide range of loads for ov dd above 2.25 v , but it is recommended to minimize the load to ensure as low transient switching currents and resulting noise as possible. in applications with a large fanout or large www.datasheet.net/ datasheet pdf - http://www..co.kr/
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 12 HMCAD1040-40 v01.0411 dual 10-bit 20/ 40 msps a /d converter capacitive loads, it is recommended to add external buffers located close to the adc chip. t he timing is described in the t iming diagram section. n ote that the load or equivalent delay on ck_ e x t always should be lower than the load on data outputs to ensure sufficient timing margins. t he digital outputs can be set in tristate mode by setting the oe _ n signal high. t he HMCAD1040-40 employs digital offset correction. t his means that the output code will be 4096 with shorted inputs. however, small mismatches in parasitics at the input can cause this to alter slightly. t he offset correction also results in possible loss of codes at the edges of the full scale range. with no offset correction, the adc would clip in one end before the other, in practice resulting in code loss at the opposite end. with the output being centered digitally, the output will clip, and the out of range fags will be set, before max code is reached. when out of range fags are set, the code is forced to all ones for overrange and all zeros for underrange. data format selection t he output data are presented on offset binary form when df r m t is low (connected to ovss ). s etting df r m t high (connected to ov dd) results in 2s complement output format. details are shown in table 3. t able 3: data format description for 2 v pp full scale range differential input v oltage (ipx - i n x) o utput data: dx_9 : dx_0 (df r m t = 0, offset binary) o utput data: dx_9 : dx_0 (df r m t = 1, 2's complement) 1.0 v 11 1111 1111 01 1111 1111 +0.24m v 10 0000 0000 00 0000 0000 -0.24m v 01 1111 1111 11 1111 1111 -1.0 v 00 0000 0000 10 0000 0000 reference voltages t he reference voltages are internally generated and buffered based on a bandgap voltage reference. n o external decoupling is necessary, and the reference voltages are not available externally. t his simplifes usage of the adc since two extremely sensitive pins, otherwise needed, are removed from the interface. operational modes t he operational modes are controlled with the pd_ n and s lp_ n pins. if pd_ n is set low, all other control pins are overridden and the chip is set in power down mode. in this mode all circuitry is completely turned off and the internal clock is disabled. hence, only leakage current contributes to the power down dissipation. t he startup time from this mode is longer than for other idle modes as all references need to settle to their fnal values before normal operation can resume. t he s lp_ n bus can be used to power down each channel independently, or to set the full chip in s leep mode. in this mode internal clocking is disabled, but some low bandwidth circuitry is kept on to allow for a short startup time. however, s leep mode represents a signifcant reduction in supply current, and it can be used to save power even for short idle periods. t he input clock should be kept running in all idle modes. however, even lower power dissipation is possible in power down mode if the input clock is stopped. in this case it is important to start the input clock prior to enabling active mode. startup initialization t he HMCAD1040-40 must be reset prior to normal operation. t his is required every time the power supply voltage has been switched off. a reset is performed by applying power down mode. wait until a stable supply voltage has been reached, and pull the pd_ n pin for the duration of at least one clock cycle. t he input clock must be running continuously during this power down period and until active operation is reached. alternatively the pd pin can be kept low during power-up, and then be set high when the power supply voltage is stable. www.datasheet.net/ datasheet pdf - http://www..co.kr/
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 13 HMCAD1040-40 v01.0411 dual 10-bit 20/ 40 msps a /d converter o utline drawing t able 4. 9x9mm qf n (64 pin l p9) dimensions s ymbol millimeter inch min t yp max min t yp max a 0.9 0.035 a1 0 0.01 0.05 0 0.0004 0.002 a2 0.65 0.7 0.026 0.028 a3 0.2 re f 0.008 re f b 0.2 0.25 0.3 0.008 0.01 0.012 d 9.00 bsc 0.354 bsc d1 8.75 bsc 0.344 bsc d2 3.79 3.99 4.19 0.149 0.157 0.165 l 0.3 0.4 0.5 0.012 0.016 0.02 e 0.50 bsc 0.020 bsc ? 1 0 12 0 12 f 1.9 0.075 g 0.24 0.42 0.6 0.0096 0.0168 0.024 www.datasheet.net/ datasheet pdf - http://www..co.kr/
for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 978-250-3343 tel ? 978-250-3373 fax ? order on-line at www.hittite.com application support: apps@hittite.com a / d converters - s m t 0 0 - 14 HMCAD1040-40 v01.0411 dual 10-bit 20/ 40 msps a /d converter package i nformation part number package body material lead finish msl [1] package marking [2] HMCAD1040-40 r oh s -compliant low s tress injection molded plastic 100% matte s n level 2a a s d0400 xxxx xxxx [1] m s l, peak t emp: t he moisture sensitivity level rating classifed according to the j e d e c industry standard and to peak solder temperature. [2] proprietary marking xxxx, 4-digit lot number xxxx www.datasheet.net/ datasheet pdf - http://www..co.kr/

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